1. Field of the Invention
The present invention relates to a microprocessor unit (called the MPU hereunder where appropriate) having an interrupt mechanism.
2. Description of the Prior Art
Recent advances in LSI (large scale integration) technology have led to a growing number of LSI applications such as those in which a single LSI chip constitutes a computer system and those in which the so-called custom LSI chip incorporates a central processing unit (CPU). Such diverse LSI applications comprise in a variety of ways a microprocessor unit that not only executes a large number of commands in a predetermined sequence; the MPU also has an interrupt mechanism that generally branches to an unsequenced address upon receipt of an interrupt signal. Where a plurality of interrupt conditions exist, a plurality of interrupt input terminals are provided so that the branch destination is varied depending on which interrupt input terminal has received an interrupt signal. Alternatively, the branch destination is determined by the interrupt vector fetched during an interrupt acknowledgment cycle in effect when the interrupt signal is input.
FIG. 4 is a basic constitution of a conventional microprocessor (MPU) with a memory, FIG. 5 is an address map of a memory area containing commands, FIG. 6 is a timing chart in effect when an interrupt signal is input during an execution sequence of an MPU, and FIG. 7 is a timing chart in effect when the interrupt routine of the MPU is terminated during the execution sequence of the MPU.
As shown in FIG. 4, the microprocessor 10 includes internal registers 12, an arithmetic logic unit (ALU) 14, a program counter (PC) 16, a stack pointer 18, an interrupt vector (IV) 20, a multiplexer (MPX) 22 for selecting address inputted to a memory 30 and an interrupt control circuit 24 for receiving an interrupt signal INT.sub.--.
What follows is a brief description of how an interrupt illustratively takes place. Only one interrupt is assumed to occur in this example for the sake of simplicity.
The main routine is stored in a region including addresses 1234 and 1235. The interrupt routine is stored at address 2000 and subsequent addresses. Addresses FFFE and FFFF are used as a stack area in which to save the content of the program counter PC upon interrupt.
In FIGS. 6 and 7, CLK stands for a clock signal, MRD.sub.-- for a memory read signal, MWR.sub.-- for a memory write signal, AD for an address signal, DATA for a data signal, PC for a program counter contents, and INT.sub.-- for the interrupt signal.
Suppose that, as shown in FIG. 6, the interrupt signal INT.sub.-- is asserted (i.e., brought Low) while the main routine command held at address 1234 is being executed. In that case, the interrupt acknowledgment cycle is entered when the command at address 1234 has ended. The low and high-order bytes of the program counter PC are saved respectively to addresses FFFF and FFFE. When the command at address 1234 is executed, the content of the program counter PC points to the next address 1235. Thus the low-order byte "35" of the program counter PC is saved to address FFFF and the high-order byte "12," to address FFFE. The save operation is followed by an interrupt process branching to address 2000, i.e., the first address of the interrupt routine.
When the interrupt routine is terminated, the data "35" and "12" saved respectively at addresses FFFE and FFFF are read therefrom and placed in the program counter PC. The address number pointing to address 1235 is then output so that execution of the main routine is resumed from address 1235.
In addition to a normal interrupt function that may be utilized by the user at his discretion, some MPU's have the so-called debug-dedicated interrupt function. The debug-dedicated interrupt function, usually not for use by the user, is a function used by a debugging apparatus incorporating debugging software. The debugging apparatus, illustratively called an incircuit emulator, is designed to debug user-generated programs. There should be no change in the execution status of the user-generated program regardless of debug interrupt being effected or not. To keep the user from becoming aware of debug interrupt requires that, at the end of the interrupt process handling the debug interrupt, there be restored the same internal status as that in effect when the debug interrupt in question was accepted.
Ordinary MPU's have a HALT command for stopping command execution. Executing the HALT command causes the MPU to halt and to stop executing all subsequent commands.
The halt state is released either upon reset or upon interrupt. This takes place as follows: suppose that the HALT command is stored at address 1234. In that case, as described with reference to FIGS. 6 and 7, the program counter possesses the next address 1235 when execution of the HALT command has resulted in the halt state. When the interrupt routine is terminated, the command held at address 1235 is read and executed.
A problem arises if a debug interrupt occurs when the halt state is in effect upon execution of a user-generated program. That is, despite the need to restore the internal state in effect prior to the debug interrupt, the halt state is released once that interrupt takes place. As a result, the halt state before the interrupt cannot be resumed.
One conventional solution of the above problem is to devise circuitry whereby the circuit operation is changed only if a debug interrupt is accepted during execution of the HALT command; the content of the program counter is then decremented by 1 before being saved into a stack.
One disadvantage of this solution is the need for special hardware by which to decrement the content of the program counter. This results in a growing scope of the circuit configuration involved.